1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, in particular to a method for fabricating a semiconductor device in which circuit elements such as transistors are electrically isolated from each other by trench isolation regions.
2. Description of the Related Art
In a semiconductor device in which a large number of circuit elements are formed on a semiconductor substrate, it is required to electrically isolate element formation regions in which the elements are to be formed from each other. A trench isolation structure is widely used as such isolation means, because the trench isolation region itself can be extremely small in area. In this structure, a trench is formed in portions of the semiconductor substrate that are allocated for isolation regions, and then buried with an insulating film.
It was, however, reported by the IEEE IEDM (International Electron Device Meeting) Technical Digest (1999, pp. 827-830) that a stress applied from the trench isolation regions to the element formation regions deteriorates the electric characteristics of the elements formed therein. One of the major origins of such stress is due to an expansion or shrinkage of the insulating film filling the trench, that is caused by later thermal treatments such as a heat treatment for an improvement in a quality of the insulating film filling the trench (called hereinafter xe2x80x9ctrench insulating filmxe2x80x9d), a thermal oxidation for forming a gate oxide film and so on, and an annealing treatment for activating ion-implanted impurities.
There have been proposed two countermeasure methods for suppressing such stress. The first one is to attempt not to transmit the stress due to the expansion and/or shrinkage of the trench insulating film to the element formation region. The second one is to attempt to reduce the expansion and/or shrinkage of the trench insulating film itself.
The first method is such that a stress buffer layer is formed between the trench insulating film and the element formation region, and is disclosed, for example, in Japanese Laid-open (Kokai) Patent Publication Hei 11-176924 or Hei 1-281746. Taking the 11-176924 Publication as an example, this method will be explained with reference to FIGS. 1A-1D.
As shown in FIG. 1A, a pad oxide film 12 and a pad nitride film 13 are formed on a silicon substrate 11 and a trench pattern is formed therein by use of photolithography techniques and etching techniques. The pad oxide film 12 is generally formed by thermal oxidation to relax a stress between the silicon substrate 11 and the pad nitride film 13.
Next, as shown in FIG. 1B, using a pad nitride film pattern as a mask, the silicon substrate 11 is etched to form a trench T. Subsequently, in order to recover crystal defects of the substrate 11 around the trench T, which are generated during etching, a thermal oxide film 14 is formed on the side walls and the bottom of the trench T. Then, in accordance with the first method, a silicon nitride film 15 is deposited as a buffer layer for the purpose of absorbing the stress given by the trench insulating film that will be formed in a subsequent step.
After that, as shown in FIG. 1C, the inside of the trench T is buried with a high density plasma CVD oxide film 16, followed by performing the CMP (Chemical Mechanical Polishing) to leave the high density plasma CVD oxide film in the trench T.
Subsequently, as shown in FIG. 1D, the pad nitride film 13 and the pad oxide film 12 are removed by wet etching to expose active regions. After that, it will be continued to a transistor device forming process.
On the other hand, the second method is to fill the trench with a plurality of insulating films that are different in composition ratio of film materials from each layer. This method is disclosed, for example, in Japanese Laid-open (Kokai) Patent Publication Hei 5-304205 or 9-260484, and will be explained referring to FIG. 2A and FIG. 2B. These figures are entered in the Hei 5-304205 Publication.
As shown in FIG. 2A, a trench pattern is formed in a silicon substrate 21 and a thermal oxide layer 22 is formed on the side walls and the bottom of the trench. Then, a first silicon nitride layer 23 which is silicon-rich and has relatively less stress and higher conductivity is deposited on the oxide layer. Subsequently, a second silicon nitride layer 24 which has a nearly stoichiometric composition ratio and has relatively larger stress and lower conductivity is fully buried in the trench. Then, as shown in FIG. 2B, all film layers except in the trench are removed using the CMP technique and a wet etching technique to expose active regions. The layers 23 and 24 may expand or shrink in opposite direction to each other.
The present inventor has, however, recognized that there are significant problems with both of the above methods. That is, in the first method, as shown in FIG. 1D, the volume of the high density plasma CVD oxide film 16 as an insulating film inside the trench T is much larger than that of the buffer layer 15. For this reason, the buffer effect is not sufficient to maintain desired electrical characteristics of the elements. In particular, the high density plasma oxide film, that is suitable to fill without void such a fine or narrow trench as having sub-micron width for realizing the high integration and fine patterns, presents a large compressive stress. Therefore, the thin buffer layer does not have a sufficient buffer effect. If the buffer layer is formed thick, such thick layer no longer serves as a buffer layer. Rather, it constitutes apart of the trench insulating film.
It is to be noted that since the high density plasma insulation layer is formed by a high density plasma CVD method in which deposition and sputter etching occurs mutually, the high density plasma insulation layer is clearly distinguished from an ordinary plasma CVD insulating film in aspect of deposition process/mechanism. The high density plasma CVD insulating film can completely fill or bury a trench having a width of 0.5 xcexcm or less without void. On the other hand, the trench employing the ordinary plasma CVD insulating film as the trench insulating film is almost always accompanied with a void. Characteristics of the high density plasma CVD insulating film and the differences thereof from the ordinary plasma CVD insulating film are described in the IEEE IEDM Technical Digest (1996, pp. 841-844).
In the second method, it is difficult to control the composition ratio of film materials in each layer to a desired value. The reproducibility is thus poor in this method. Furthermore, this method uses an insulating film other than a high density plasma CVD method is employed, the trench insulating film can not bury a trench having a width of 0.5 xcexcm or less without generation of any void.
Therefore, an object of the present invention is to provide an improved method of fabricating a semiconductor device having a trench isolation structure.
Another object of the present invention is to provide a method of fabricating a semiconductor device in which the stress applied to each element formation region from each trench isolation region is efficiently suppressed.
Still another object of the present invention is to provide a method of fabricating a semiconductor device having a trench isolation structure wherein a trench with a sub-micron width of 0.5 xcexcm or less is filled with an insulating film without generation of a void in the trench and with suppressing stress to an element formation region surrounded by the trench.
Yet another object of the present invention is to provide method of fabricating a semiconductor device having a trench isolation structure with controllability and reproducibility.
A method according to the present invention is featured in that an insulating layer, which is to fill a trench selectively provided in a semiconductor substrate, is formed through at least two, separate deposition steps, and a heat treatment is performed after the first deposition step and before the second deposition step.
In other words, the trench insulating layer is not formed at single deposition step, but is performed at least two, separate deposition steps with the heat treatments conducted between these deposition steps. As a matter of course, the insulating film deposited through the first deposition step does not completely fill the trench, leaving a space in the trench, and under this condition, the heat treatment is carried out. By this heat treatment, the trench insulating film formed through the first deposition shrinks or expands. However, in this case, the insulating film is physically free on the side of surface which is exposed to the space in the trench. Accordingly, there is a degree of freedom in the rearrangement of atoms in the insulating film, and the application of the stress due to the expansion or shrinkage of the trench insulating film to the element formation region can be effectively prevented. It is further to be noted that the trench insulating film falls essentially in a thermally stable state after the expansion or shrinkage during the heat treatment. Therefore, even if later thermal treatments such as a thermal oxidation process for forming a gate oxide film and so on and an annealing treatment for activating ion-implanted impurities are carried out, re-expansion or re-shrinkage of the trench insulating film does not substantially occur.
Thus, the method according to the present invention is to make a part or a great part of the trench insulating layer thermally stabilized prior to the trench being completely filled with an insulating film. As a result, the stress applied to each element formation region from each trench isolation region is efficiently suppressed during a further thermal treatment.
With respect to the trench insulating film that has been formed through the final deposition, it may generate some stress during the heat treatment applied thereto because there is no such space as described above. However, such stress can be confined within the level not to cause the substantive deterioration of the characteristics of elements, because the volume of the insulating film deposited at the last deposition step is relatively small.
It is convenient to use a high density plasma CVD insulating film, particularly a high density plasma CVD silicon oxide film, as an insulating film that is to fill the trench. Thus, at least two times of deposition of a high-density plasma silicon oxide film are carried out with performing a heat treatment after each deposition. As a result, the trench with a sub-micron width such as 0.5 xcexcm or less is filled completely with the high-density plasma silicon oxide film without generation of any void in the trench and with substantive suppression of stress applied to the element formation region.